In a quest for faster and smaller footprint ESD protection devices for I/O pins, gated diodes as illustrated in FIG. 2 are being used instead of conventional to composite diodes as shown in FIG. 1. The conventional composite diode of FIG. 1 includes a p+ region 100 separated from an n+ region 102 by a composite 104, which in this case is 0.28 um in length. The gate diode of FIG. 2, also includes a p+ region 200 and an n+ region 202 but in this case the p+ and n+ regions are spaced apart by a gate 204. TCAD simulations have shown definite advantages of gated diodes over composite diodes, including improved forward recovery and ESD current. In fact, experimental results have shown a 40% increase in forward current over conventional composite diodes.
Nevertheless, these diodes have their own drawbacks, largely due to long term reliability of the gate oxide due to hot carrier degradation, resulting in reduced voltage tolerance. Essentially the voltage is limited by the maximum gate voltage of the corresponding standard NMOS and PMOS devices in the process as defined by the gate oxide.
The present invention seeks to address this problem by providing a gated diode with higher voltage tolerance.